The present invention relates to the field of circuit simulation, and more precisely to enabling circuit designers to more easily and immediately ensure that predetermined voltages are properly applied to circuit components during simulated stress testing.
Yield and reliability are two factors affecting the profitability of semiconductor manufacturing. Yield refers to the percentage of integrated circuits that perform properly after fabrication, while reliability refers to the likelihood an integrated circuit will fail only after some useful lifetime. Integrated circuit components tend to fail primarily from early “infant mortality” or from later “wear out”, with a relatively low failure rate in between. Reduction of early failures is desirable to improve integrated circuit reliability.
One way to reduce early failures is to apply “stress” testing to speed up the deterioration of electronic devices with latent defects. The concept is to effectively accelerate through the early life of such devices while they are still in the factory. Integrated circuits that would normally succumb to infant mortality after sale are instead made to fail more quickly, so they may be screened (e.g., identified and discarded) prior to shipment. The integrated circuits that pass the stress testing process may begin their operation with a failure rate much lower than that typical of unscreened newly manufactured integrated circuits.
The industry standard methods for such screening have included “burn in” and high voltage screening. Burn in may subject new integrated circuits to operation at elevated temperatures, typically for days. Burn in is effective to varying degrees for almost all circuits and the many physical mechanisms underlying premature failure. This screening option is relatively costly however, with added manufacturing costs typically ranging from five percent to forty percent of the total product cost, depending on the burn in time, integrated circuit quality, and product complexity.
High voltage screening, often referred to as extreme voltage screening or voltage stress testing, aims to similarly improve integrated circuit quality without requiring the higher cost burn in process. Voltage stress testing may comprise the application of significantly higher supply and input voltages than normal to a circuit, typically for a few seconds during routine production functionality testing, to activate latent defects. Voltage stresses may be applied in dynamic pulse patterns that are most likely to activate defects.
Engineers have used voltage stress testing to enhance the reliability of digital integrated circuits. More recently, engineers have also applied voltage stress testing to analog integrated circuits, though with some difficulty. Applying stress test voltages to the external pins of analog integrated circuits does not necessarily cause the internal devices to be subjected to desired overvoltages. On-chip voltage regulators may prevent the externally applied stress voltages from propagating to desired internal nodes because they regulate the desired stress voltages back down to normal non-stress levels.
Accordingly, the inventors have developed a solution to address this problem.